1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of stacked semiconductor chips and a method of manufacturing the semiconductor device.
2. Description of the Related Art
In recent years, a multiple chip package (MCP) in which a plurality of semiconductor chips are stacked has attracted attention as a technique to reduce the package area while reducing the manufacturing cost. An MCP in which two semiconductor chips are stacked will be described by way of example. First, the first semiconductor chip is mounted on a package substrate, and electrodes of this semiconductor chip and electrodes on the package substrate are connected to each other by wires. The second semiconductor chip is thereafter mounted on the first semiconductor chip with an adhesive, and electrodes of the second semiconductor chip and electrodes on the package substrate are connected to each other by wires.
With the MCP, there is a problem of contact between wires that led out from the electrodes of the semiconductor chip on the lower layer side and the surface of this semiconductor chip.
Japanese Patent Laid-Open Nos. 2004-312008, 2008-198909 and 11-135539 disclose means for preventing such an undesirable contact.
According to Japanese Patent Laid-Open No. 2004-312008, an insulating supporting structure is provided on the periphery of the semiconductor chip on the lower layer side to prevent undesirable contact between wires and the semiconductor chip.
According to Japanese Patent Laid-Open No. 2008-198909, wires from the semiconductor chip on the lower layer side are embedded in a resin interposed between the semiconductor chips in the upper and lower layers.
According to Japanese Patent Laid-Open No. 11-135539, wires are sandwiched in a two-layer polyimide tape in a structure that as different from the MCP structure.
Recent semiconductor devices are operated at higher speeds and there is a demand for minimizing parasite capacitance of the wire or the like. In particular, MCPs such as those described above are of such a construction that the parasitic capacitance of the wires from the semiconductor chip on the lower layer side can be increased due to passage of the wires between the two semiconductor chips. However, any of Japanese Patent Laid-Open Nos. 2004-312008, 2008-198909 and 11-135539 is not concerned with this point.